HOME

Top 10 List of Week 04

1. CPU Protection
   CPU protection is referred to as we can not give CPU to a process forever, it should be for some limitedtime otherwise other processes will not get the chance to execute the process. So for that, a timer is used to get over from this situation. which is basically give a certain amount of time a process and after the timer execution a signal will be sent to the process to leave the CPU. hence process will not hold CPU for more time.

2. Memory Protection
   In memory protection, we are talking about that situation when two or more processes are in memory and one process may access the other process memory. and to protecting this situation we are using two registers as Bare Register and Limit Register.

3. Base and Limit Registers
   Base register contains value of smallest physical address while Limit register contains range of logical addresses – each logical address must be less than the limit register. Basically, Bare register store the starting address of program and limit register store the size of the process, so when a process wants to access the memory then it is checked that it can access or can not access the memory.

4. I/O Protection
   When we’re ensuring the I/O protection, then some cases will never have occurred in the system such as Termination I/O of other process, View I/O of other process, or Giving priority to a particular process I/O. We know that when an application process wants to access any I/O device it should be done through system call so that the Operating system will monitor the task.

5. Address Binding
   Address binding is part of computer memory management and it is performed by the operating system on behalf of the applications that need access to memory. Address binding allocates a physical memory location to a logical pointer by associating a physical address to a logical address, which is also known as a virtual address.Basically, address binding is the process of mapping from one address space to another address space.

6. Logical Address
   Logical address is a virtual address as it does not exist physically, therefore, it is also known as Virtual Address and is also generated by CPU while a program is running. This address is used as a reference to access the physical memory location by CPU. The hardware device called Memory-Management Unit is used for mapping logical address to its corresponding physical address.

7. Physical Address
   Physical Address identifies a physical location of required data in a memory. The user never directly deals with the physical address but can access by its corresponding logical address. The user program generates the logical address and thinks that the program is running in this logical address but the program needs physical memory for its execution, therefore, the logical address must be mapped to the physical address by MMU before they are used. The term Physical Address Space is used for all physical addresses corresponding to the logical addresses in a Logical address space.

8. Big Endian and Little Endian
   A topic that has been previously touched on in previous semesters in PSD and IDS, Big-endian is an order in which the “big end” (most significant value in the sequence) is stored first (at the lowest storage address). Little-endian is an order in which the “little end” (least significant value in the sequence) is stored first.

9. Fragmentation
   Fragmentation is a phenomenon in which storage space is used inefficiently, reducing capacity or performance and often both. Basically, creating wasted spaces. There are 3 types of fragmentation: Internal Fragmentation, when more computer memory is sometimes allocated than is needed. External Fragmentation, when free memory is separated into small blocks and is interspersed by allocated memory. Data Fragmentation, when a collection of data in memory is broken up into many pieces that are not close together.

10. MMU (Memory Management Unit)
    A memory management unit (MMU) is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.